1. Field of the Invention
The primary purpose of transmission codes is to transform the frequency spectrum of a serial data stream so that clocking can be recovered readily and AC coupling is possible. The code must also provide special characters outside the data alphabet for functions such as character synchronization, frame delimiters and perhaps for abort, reset, idle, diagnostics, etc. Codes are also used, often in combination with signal waveform shaping, to adapt the signal spectrum more closely to specific channel requirements. In most cases a reduction in bandwidth by constraints on both the high and the low frequency components is desirable to reduce distortion in the transmission media, especially electromagnetic cables, or in the band limited receiver, and to reduce the effects of extrinsic and intrinsic noise.
Another aspect of codes is their interaction with noise and errors in the line digits. The redundancy associated with line codes can be used to supplement other error detection mechanisms or to monitor the quality of the channel with a minimal amount of circuitry.
Such codes generally exhibit the undesirable feature of enlarging error bursts in the decoded data, making detection by a cyclic redundancy check more difficult. A good transmission code should minimize these effects.
For fiber optic links and intra-establishment wire links, interest centers for many reasons on the family of two-level codes. For wire links one prefers codes with no DC and little low frequency content in order to DC isolate the transmission line from the driver and receiver circuitry, usually by transformers, and to reduce signal distortion on the line. Although these factors do not apply to the fiber optic case, good low frequency characteristics of the code are helpful for a number of reasons.
The high gain fiber optic receivers need an AC coupling stage near the front end. The control of the drive level, receiver gain, and equalization is simplified and the precision of control is improved, if it can be based on the average signal power, especially at top rates. DC restore circuits tend to lose precision with rising data rates and cease to operate properly below the maximum rates for other circuits required in a transceiver. Finally, if the time constants associated with the parasitic capacitances at the front end of a receiver are comparable to or longer than a baud interval, a signal with reduced low frequency content will suffer less distortion and will enable many links to operate without an equalizing circuit.
The Manchester and related codes are simple two-level codes and solve the clocking and low frequency problems very well. They translate each bit into two bits for transmission and are a good choice whenever the high clocking rates cause no problems in the logic or analog circuits, the transducers or on the transmission line. They also reduce the data transmission rate by a factor of two since they encode 2 bits for every data bit (i.e., rate 1/2).
Simple 5B/6B codes translate 5 binary bits into 6 binary digits and raise the number of information bits transmitted per baud interval to 0.833. Unfortunately, the implementation of a 5B/6B code in a byte-oriented (8 bit) system causes burdensome complexities. If the encoding and decoding is done serially, most of the circuits needed have to operate at the baud rate, which sometimes is at the technology limits. Also, there is no simple relationship between the byte clock and the coder clock. Finally, if the frames are not multiples of 5 bytes, the character boundaries will not align with the frame boundaries, which is unattractive, whether corrected or not. If the coding and decoding is done in parallel, there is no simple mechanism to align a byte parallel interface with a 5B/6B coder; the most straightforward way requires shift registers operating at the baud rate.
Background Art
An article by T. Horiguchi and K. Morita, "An Optimization of Modulation Codes in Digital Recording," IEEE Transactions on Magnetics, Vol. MAG-12, No. 6, November 1976, page 740, is in essence a survey article which cites a great many possible formats for run length limited codes having various d, k values and varying coding rates. It is cited for reference purposes, it being noted that there are no codes suggested in this article having parameters even remotely approaching those of the presently disclosed coding system. Similarly the article is not concerned with maintaining dc balance in the resulting code stream.
An article entitled "Encoding/Decoding for Magnetic Record Storage Apparatus," by R. C. Kiwimagi, IBM Technical Disclosure Bulletin, Vol. 18, No. 10, March 1976, page 3147, discloses a (0,6) rate 4/5 run length limited code which attempts to maintain a dc balance. It is noted that this code is significantly different from the present coding system in that both the codes produced and the coder configuration are quite different than that of the present invention even if two of the rate 4/5 coders of this reference were connected in parallel to perform an 8/10 coding operation.
U.S. Pat. No. 3,798,635 of Candiani, entitled "Channel Monitor for Depressed-Code PCM Transmission System," discloses an 8 bit to 12 bit code expansion system. It does not disclose the present system's dc balanced run length limited codes.
U.S. Pat. No. 3,577,142 of McMillin, entitled "Code Translation System," discloses a system for translating a 12 bit code into a 8 bit code and is cited as background but does not relate to the present run length limited coding systems.
U.S. Pat. No. 3,594,560 of Stanley, entitled "Digital Expander Circuit," discloses a simple expander for precompressed data and is similar to the two patents cited above representatives of the state of the art and is not otherwise related to run length limited coding systems.
An article entitled "Binary Codes Suitable for Line Transmission," Electronics Letters, Vol. 5, No. 4, pp. 79-81, 20 February 1969, generally describes a DC balanced rate 5/6 and 3/4 codes but does not suggest combining same nor does it show similar embodiment circuitry.
No prior art is known to the inventors, which partitions an 8 bit code into 5 bit and 3 bit sub-blocks for encoding purposes nor discloses coding circuitry for concurrently doing the logic manipulations for computing the proper code words, the disparity of said code words and, depending upon the disparity of the preceeding sub-block, concurrently determining whether a given code word or its complement will be coded.